The present disclosure relates to processors and more specifically, to methods, systems and computer program products for managing a free list of available resources in a processor to decrease control complexity and reduce power consumption.
Modern processors generally support simultaneous multi-threading to increase throughput. Processor throughput may be measured by the useful execution of a number of instructions per thread for each stage of a pipeline of the processor. Various techniques are used to take advantage of instruction level parallelism and to increase the throughput of the processor. However, many of these techniques add more hardware and more depth to the pipelines of the processor. In addition, control complexities and data dependencies associated with many such techniques may reduce a maximum throughput of the processor.
Speculative execution of instructions can be used to perform parallel execution of instructions despite dependencies in the source code. However, the execution techniques used to perform speculative execution may utilize a relatively large number of physical registers, which are used to store the state of intermediate results from instruction execution. Typically, a free list is used to keep track of which physical registers are not currently in use. These free physical registers are available for use by incoming instructions. As the number of physical registers increase, the number of storage elements used for the free list and for identifying recently retired physical register identifiers increases. As a result, the power required for the maintenance of these physical registers increases.
Current techniques for managing a free list for multi-threaded processors include creating a buffer of available physical registers for each pipeline and committing each available physical registers to one of the pipelines. The buffers are then independently managed and physical registers are dispatched from the buffer for each pipeline to each thread as needed.